CMOS GATES-2

Posted by Mithila


NOR GATE IMPLEMENTATION:

When both the inputs are low, the pmos devices are on as well as both the nmos devices are off. Hence output becomes logic high.


When either of the inputs is high, i.e. A/B is at high logic, the nmos device mn1/mn2 turns on and the pmos mp1/mp2 turns off, hence the output Y is at logic low.

When both the inputs are high, both the nmos devices conduct. As both the pmos devices are off; output becomes logic low.

The truth table is as follows:

 A        B        Y
--------------------
 0         0         1
 0         1         0
 1         0         0
 1         1         0

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