LIFE IS WHAT WE DREAM IT....!!!

NAND GATE IMPLEMENTATION:


A and B are the two inputs and Y is the output. If either of the inputs is low, i.e. A/B is at low logic, the device mn1/mn2 is off while the pmos mp1/mp2 is on, hence the output Y is at high logic.

When both the inputs are high, the nmos devices are turned on and form a low resistive path from output Y to ground. With the parallel pmos devices off, the output becomes logic low.



The truth table is as follows:

A       B       Y
----------------
0        0        1
0        1        1
1        0        1
1        1        0